A dynamic random access memory, which is typically comprised of an array of a large number of cells, each being made up by a capacitor for data retention and a transistor connected between a bit line and the capacitor and having a gate connected to a word line, is able to have large amount of memory capacity. However, in dynamic random access memory, the data is retained in the capacitor, and hence a refresh operation, which comprises the steps of amplifying memory cell data by a sense amplifier via bit line at a preset period and writing the data again from the bit line to the memory cell, is needed for data retention.
A refresh address is generated by a counter which receives a refresh clock signal generated based on e.g. a timer and counts up the clock signal received. The refresh address is supplied to a multiplexer which selects one between a row address of a normal access and the refresh address. More specifically, during the refresh operation, the multiplexer selects the refresh address, based on a refresh control signal, and the so selected refresh address is supplied to an X-decoder. A word line selected by the X-decoder is activated, and a sense amplifier is also activated to carry out refreshing. The word line selected is subsequently deactivated.
As to the refresh control of a cell having a short refresh period, that is, having a data retention time shorter than in other cells, the following two techniques have so far been proposed.
For example, Patent Document 1 (JP Patent Kokai Publication No. JP-A-62-223893) discloses a configuration in which memory cells are periodically refreshed based on a counter operation. The row address with a shorter refresh period is refreshed simultaneously with the row address, which is a refresh address generated by the counter, whereby the row address with a shorter refresh period is refreshed with the shorter period, as shown in FIG. 1A. For example, a refresh address 0 is refreshed with a period equal to one-half the refresh period.
In this configuration, the other row address in addition to the refresh address need to be refreshed simultaneously. Since two word lines are refreshed simultaneously, the sense noise in the DRAM is doubled. Hence, a variety of circuits in the memory device, such as power supply, ground lines or boost level supply circuit, need to be enhanced in order to cope with the doubled sense noise, thus enlarging the circuit scale.
Moreover, the condition of the above-described simultaneous refresh operation differs from that of the normal refresh operation, and hence, in a memory having a high-speed input/output circuit, such problems as deteriorated characteristics of the input/output circuit may arise exclusively during the simultaneous refresh operation.
The Patent Document 2 (JP Patent Kokai Publication No. JP-A-8-306184) discloses a configuration in which the refresh operation may be carried out in keeping with the information retention time of the memory cells. More specifically, a first pulse, corresponding to the refresh period which is set to be shorter than the shortest memory cell information retention time (data retention time), is generated. The first pulse is counted by a refresh address counter to generate a refresh address. A second pulse signal is generated by frequency-dividing a carry signal which is generated by the refresh address counter for one cycle of the refresh operation (divided pulse signal). The refresh period setting information, associated either with the short period of the first pulse or with the long period of the second pulse is stored in a storage circuit every plural word lines allocated to theses refresh addresses. The refresh operation for the memory cells, carried out based on the refresh address is rendered valid or invalid, for each word line, in association with the refresh period setting information stored in the storage circuit. The refresh period setting information is rendered invalid by the second pulse signal. In this DRAM, the first pulse, which is associated with the refresh period, and which selected to be shorter than the shortest data retention time, is generated, such that it is necessary to generate a clock signal having a period adjusted so as to hold data even in the memory cells with the shortest refresh period. In DRAMs, since the refresh trigger command period from a controller is fixed, it is generally difficult to generate such a clock signal from one particular DRAM to another.
The refresh operations may be carried once every two periods of the refresh trigger command from the controller, as shown in FIG. 1B. Although this may be efficacious in suppressing the power usage, it is not possible to relieve the memory cells with the short refresh period.
[Patent Document 1]
JP Patent Kokai Publication No. JP-A-62-223893
[Patent Document 2]
JP Patent Kokai Publication No. JP-A-8-306184